Magnetic memory device using SOI substrate and method of manufacturing the same

ABSTRACT

A magnetic memory device includes an SOI substrate having a first semiconductor layer, a first insulating film formed on the first semiconductor layer, and a second semiconductor layer formed on the first insulating film, an element isolation insulating film formed selectively in the second semiconductor layer extending from a surface of the second semiconductor layer with a depth reaching the first insulating film, a switching element formed in the second semiconductor layer, a magneto-resistive element connected to the switching element, a first wiring extending in a first direction at a distance below the magneto-resistive element, and a second wiring formed on the magneto-resistive element and extending in a second direction different from the first direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2001-342289, filed Nov.7, 2001, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to a magnetic memorydevice and a method of manufacturing the memory device. This inventionrelates more particularly to a magnetic random access memory (MRAM)wherein a memory cell is formed using a magnetic tunnel junction (MTJ)element that stores information “1” or “0” on the basis of a tunnelmagneto-resistive (TMR) effect.

[0004] 2. Description of the Related Art

[0005] In these years, many kinds of memories that store informationbased on new principles have been proposed. One of them is a magneticrandom access memory (MRAM) using a tunneling magneto-resistive (TMR)effect. The MRAM is disclosed, for example, in ISSCC2000 TechnicalDigest, p. 128, Roy Scheuerlein et al., “A 10 ns Read and WriteNon-Volatile Memory Array Using a Magnetic Tunnel Junction and FETSwitch in each Cell.”

[0006]FIGS. 15A, 15B and 15C are cross-sectional views of a magnetictunnel junction (MTJ) element of a prior-art magnetic memory device. TheMTJ element used as a memory element of the MRAM will now be described.

[0007] As is shown in FIG. 15A, an MTJ element 31 has such a structurethat an insulating layer (tunnel junction layer) 42 is interposedbetween two magnetic layers (ferromagnetic layers) 41 and 43. In theMRAM, the MTJ element 31 stores information “1” or “0”. The information“1” or “0” is determined, depending on whether the directions ofmagnetization of the two magnetic layers 41 and 43 in the MTJ element 31are parallel or anti-parallel. The term “parallel” in this context meansthat the directions of magnetization of two magnetic layers 41 and 43are the same, and “anti-parallel” means that the directions ofmagnetization of two magnetic layers 41 and 43 are opposite to eachother.

[0008] Specifically, when the directions of magnetization of twomagnetic layers 41 and 43 are parallel, as shown in FIG. 15B, the tunnelresistance of the insulating layer 42 interposed between the twomagnetic layers 41 and 43 takes a minimum value. This state correspondsto, for example, “1”. On the other hand, when the directions ofmagnetization of two magnetic layers 41 and 43 are anti-parallel, asshown in FIG. 15C, the tunnel resistance of the insulating layer 42interposed between the two magnetic layers 41 and 43 takes a maximumvalue. This state corresponds to, for example, “0”.

[0009] Normally, an anti-ferromagnetic layer 103 is provided on one ofthe two magnetic layers 41 and 43. The anti-ferromagnetic layer 103 is amember for fixing the direction of magnetization of one magnetic layer41, thus permitting easy rewriting of information by merely changing thedirection of magnetization of the other magnetic layer 43 alone.

[0010]FIG. 16 shows MTJ elements arranged in a matrix in a prior-artmagnetic memory device. FIG. 17 shows asteroid curves in the prior-artmagnetic memory device. FIG. 18 shows MTJ curves in the prior-artmagnetic memory device. The principle of the write operation for the MTJelement will now be described in brief.

[0011] As is shown in FIG. 16, MTJ elements 31 are arranged atintersections between write word lines 28 and bit lines (data selectlines) 32, which are arranged to cross each other. A data writeoperation is performed by supplying a current to each of the write wordlines 28 and bit lines 32 and setting the directions of magnetization ofthe MTJ elements 31 in a parallel state or an anti-parallel state,making use of magnetic fields produced by the current flowing in bothlines 28 and 32.

[0012] For example, in the data write mode, the bit lines 32 aresupplied with only a current I1 that flows in one direction, and thewrite word lines 28 are supplied with a current I2 that flows in onedirection or a current I3 that flows in the other direction inaccordance with data to be written. When the write word line 28 issupplied with the current I2 that flows in the one direction, thedirection of magnetization of the MTJ element 31 is parallel (“1”state). On the other hand, when the write word line 28 is supplied withthe current I3 that flows in the other direction, the direction ofmagnetization of the MTJ element 31 is anti-parallel (“0” state).

[0013] How the direction of magnetization of the MTJ element 31 ischanged will now be described. When a current is supplied to a selectedwrite word line 28, a magnetic field Hx occurs in a longitudinaldirection, i.e. an Easy-Axis direction, of the MTJ element 31. When acurrent is supplied to a selected bit line 32, a magnetic field Hyoccurs in a transverse direction, i.e. a Hard-Axis direction, of the MTJelement 31. As a result, a composite magnetic field of the Easy-Axismagnetic field Hx and lard-Axis magnetic field Hy acts on the MTJelement 31 located at the intersection of the selected write word line28 and selected bit line 32.

[0014] In a case where the magnitude of the composite magnetic field ofthe Easy-Axis magnetic field Hx and Hard-Axis magnetic field Hy is in anoutside region (hatched region) of asteroid curves indicated by solidlines in FIG. 17, the direction of magnetization of the magnetic layer43 can be reversed. On the other hand, when the magnitude of thecomposite magnetic field of the Easy-Axis magnetic field Hx andHard-Axis magnetic field Hy is in an inside region (blank region) of theasteroid curves, the direction of magnetization of the magnetic layer 43cannot be reversed.

[0015] In addition, as indicated by solid and broken lines in FIG. 18,the magnitude of the Easy-Axis magnetic field Hx, which is necessary forvarying the resistance value of the MTJ element 31, varies depending onthe magnitude of the Hard-Axis magnetic field Hy. Making use of thisphenomenon, the direction of magnetization of only the MTJ element 31located at the intersection of the selected write word line 28 andselected bit line 32, among the arrayed memory cells, is altered, andthus the resistance value of the MTJ element 31 can be varied.

[0016] A variation ratio in resistance value of the MTJ element 31 isexpressed by an MR (Magneto-Resistive) ratio. For example, if themagnetic field Hx is produced in the Easy-Axis direction, the resistancevalue of the MTJ element 31 varies, e.g. about 17%, compared to thestate before the production of magnetic field Hx. In this case, the MRratio is 17%. The MR ratio varies depending on the properties of themagnetic layer. At present, MTJ elements with an MR ratio of about 50%have successfully been obtained.

[0017] As has been described above, the direction of magnetization ofthe MTJ element 31 is controlled by varying each of the magnitudes ofEasy-Axis magnetic field Hx and Hard-Axis magnetic field Hy and byvarying the magnitude of the composite magnetic field of the fields Hxand Hy. In this manner, a state in which the direction of magnetizationof the MTJ element 31 is parallel or a state in which the direction ofmagnetization of the MTJ element 31 is anti-parallel is created, andinformation “1” or “0” is stored.

[0018]FIG. 19 is a cross-sectional view of a prior-art magnetic memorydevice having a transistor. FIG. 20 is a cross-sectional view of aprior-art magnetic memory device having a diode. An operation of readingout information from the MTJ element will be described below.

[0019] Data read-out is effected by supplying a current to a selectedMTJ element 31 and detecting the resistance value of the MTJ element 31.The resistance value is varied by applying a magnetic field to the MTJelement 31. The varied resistance value is read out by the followingmethod.

[0020] In the example shown in FIG. 19, a MOSFET 64 is used as aswitching element for data read-out. As is shown in FIG. 19, an MTJelement 31 is connected in series to a source/drain diffusion layer 63of the MOSFET 64 in one cell. If the gate of the MOSFET 64, which is achosen one, is turned on, a current path is formed through the followingelements in the named order: a bit line 32, MTJ element 31, a lowerelectrode 30, a contact 29, second wiring 28, a contact 27, first wiring26, a contact 25, and source/drain diffusion layer 63. Thus, theresistance value of the MTJ element 31, which is connected to theturned-on MOSFET 64, can be read out.

[0021] In the example of FIG. 20, a diode 73 is used as a switchingelement for data read-out. As is shown in FIG. 20, an MTJ element 31 isconnected in series to a diode 73 within a cell, the diode 73 comprisinga P⁺ first diffusion layer 71 and an N⁻ second diffusion layer 72. Byadjusting a bias voltage so as to cause a current to flow to the diode73, which is a chosen one, the resistance value of the MTJ element 31connected to the diode 73 can be read out.

[0022] If the resistance value, which has been read out as describedabove, is low, it is determined that information “1” has been written.If the resistance value is high, it is determined that information “0”has been written.

[0023] In the prior-art magnetic memory device, the switching element isformed in a bulk substrate 61. In the magnetic memory device using thediode 73 as the switching device, as shown in FIG. 20, the N⁻ seconddiffusion layer 72 is formed to be shallower than the bottom surface ofa element isolation region 65 and the P⁺ first diffusion layer 71 isformed in a surface portion of the N⁻ second diffusion layer 72, therebyensuring electrical isolation between the present cell and adjacentcells. Hence, when the diode 73 is to be formed using the bulk substrate61, it is necessary to form a very shallow P⁺ first diffusion layer 71.However, to form a shallow P⁺ first diffusion layer 71 is difficultbecause of limitations in the process, and thus it is difficult toobtain uniform diode characteristics.

BRIEF SUMMARY OF THE INVENTION

[0024] According to a first aspect of the present invention, there isprovided a magnetic memory device comprising: an SOI substrate having afirst semiconductor layer, a first insulating film formed on the firstsemiconductor layer, and a second semiconductor layer formed on thefirst insulating film; an element isolation insulating film formedselectively in the second semiconductor layer extending from a surfaceof the second semiconductor layer with a depth reaching the firstinsulating film; a switching element formed in the second semiconductorlayer; a magneto-resistive element connected to the switching element; afirst wiring extending in a first direction at a distance below themagneto-resistive element; and a second wiring formed on themagneto-resistive element and extending in a second direction differentfrom the first direction.

[0025] According to a second aspect of the invention, there is provideda method of manufacturing a magnetic memory device, comprising: formingan SOI substrate having a first semiconductor layer, a first insulatingfilm formed on the first semiconductor layer, and a second semiconductorlayer formed on the first insulating film; forming an element isolationinsulating film selectively in the second semiconductor layer, theelement isolation insulating film extending from a surface of the secondsemiconductor layer with a depth reaching the first insulating film;forming a switching element in the second semiconductor layer; forming afirst wiring extending in a first direction; forming a magneto-resistiveelement connected to the switching element at a distance above the firstwiring; and forming a second wiring on the magneto-resistive element,the second wiring extending in a second direction different from thefirst direction.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0026]FIG. 1 is a cross-sectional view of a magnetic memory deviceaccording to a first embodiment of the present invention;

[0027]FIG. 2 is a circuit diagram of the magnetic memory deviceaccording to the first embodiment of the invention;

[0028]FIG. 3A and FIG. 3B are cross-sectional views showing an MTJelement of a single tunnel junction structure according to each ofembodiments of the present invention;

[0029]FIG. 4A and FIG. 4B are cross-sectional views showing an MTJelement of a double tunnel junction structure according to each ofembodiments of the present invention;

[0030]FIGS. 5, 6 and 7 are cross-sectional views illustratingfabrication steps of the magnetic memory device according to the firstembodiment of the invention;

[0031]FIG. 8 is a circuit diagram showing a magnetic memory deviceaccording to a second embodiment of the invention;

[0032]FIGS. 9A and 9B are cross-sectional views showing a magneticmemory device according to a third embodiment of the invention;

[0033]FIGS. 10A, 10B and 10C are cross-sectional views illustratingfabrication steps of a first method for fabricating the magnetic memorydevice according to the third embodiment of the invention;

[0034]FIGS. 11A, 11B, 11C, 11D, 11E and 11F are cross-sectional viewsillustrating fabrication steps of a second method for fabricating themagnetic memory device according to the third embodiment of theinvention;

[0035]FIG. 12 is a plan view of a magnetic memory device according to afourth embodiment of the invention;

[0036]FIG. 13A is a cross-sectional view of the magnetic memory device,taken along line XIIIA-XIIIA in FIG. 12;

[0037]FIG. 13B is a cross-sectional view of the magnetic memory device,taken along line XIIIB-XIIIB in FIG. 12;

[0038]FIG. 14 is a circuit diagram of the magnetic memory deviceaccording to the fourth embodiment of the invention;

[0039]FIGS. 15A, 15B and 15C are cross-sectional views showing aprior-art MTJ element;

[0040]FIG. 16 shows MTJ elements arranged in a matrix in the prior-artmagnetic memory device;

[0041]FIG. 17 shows asteroid curves relating to the prior-art magneticmemory device;

[0042]FIG. 18 shows MTJ curves relating to the prior-art magnetic memorydevice;

[0043]FIG. 19 is a cross-sectional view of a prior-art magnetic memorydevice having a transistor; and

[0044]FIG. 20 is a cross-sectional view of a prior-art magnetic memorydevice having a diode.

DETAILED DESCRIPTION OF THE INVENTION

[0045] Embodiments of the present invention relate to magnetic randomaccess memories (MRAMs) using as memory elements magnetic tunneljunction (MTJ) elements that make use of a tunneling magneto-resistiveeffect.

[0046] Embodiments of the invention will now be described with referenceto the accompanying drawings. In the following descriptions referring toall Figures, common parts are denoted by like reference numerals.

[0047] [First Embodiment]

[0048] In a first embodiment of the invention, a diode is formed usingan SOI (Silicon On Insulator) substrate, and a potential of a gateelectrode is fixed.

[0049]FIG. 1 is a cross-sectional view of a magnetic memory deviceaccording to the first embodiment of the invention. FIG. 2 is a circuitdiagram schematically showing the magnetic memory device according tothe first embodiment of the invention.

[0050] As is shown in FIGS. 1 and 2, the magnetic memory deviceaccording to the first embodiment employs an SOI substrate 14 comprisingfirst and second semiconductor layers 11 and 12, and a buried oxide film13 formed between the first and second semiconductor layers 11 and 12.In the SOI substrate 14, element isolation regions 15 of, e.g. an STI(Shallow Trench Isolation) structure are selectively formed from asurface of the second semiconductor layer 12 to a depth reaching theburied oxide film 13. The second semiconductor layer 12 surrounded bythe buried oxide film 13 and element isolation regions 15 is formed ineach cell. A gate electrode 17 is selectively formed over the secondsemiconductor layer 12 surrounded by these insulating films 13 and 15,with a gate insulating film 16 interposed. The gate electrode 17 isfixed at a predetermined potential, e.g. a ground potential. A P⁺ firstdiffusion layer 19 is formed in that portion of the second semiconductorlayer 12, which is near one end of the gate electrode 17, and an N⁺second diffusion layer 21 is formed in that portion of the secondsemiconductor layer 12, which is near the other end of the gateelectrode 17. Thus, a so-called gate-control-type diode 10 is formed onthe SOI substrate 14.

[0051] An MTJ element 31 is connected in series to the first diffusionlayer 19 of diode 10 via first to fourth contacts 23 a, 25, 27 and 29,first to third wirings 24 a, 26 and 28 a and a lower electrode 30. A bitline 32 is connected to the MTJ element 31. A write word line 28 bformed of the third wiring is provided at a distance below the MTJelement 31.

[0052] A first contact 23 b and a first wiring 24 b are connected to thesecond diffusion layer 21 of diode 10. The first wiring 24 b isconnected to a peripheral circuit (not shown).

[0053] The MTJ element 31 comprises at least three layers, i.e., amagnetically fixed layer (magnetic layer) 41 whose magnetizationdirection is fixed, a tunnel junction layer (nonmagnetic layer) 42, anda magnetic recording layer (magnetic layer) 43 whose magnetizationdirection is reversible. This MTJ element 31 can have either a singletunnel junction structure comprising a single tunnel junction layer 42,or a double tunnel junction structure comprising two tunnel junctionlayers. Examples of the single and double tunnel junction structureswill be described below.

[0054] An MTJ element 31 with the single tunnel junction structure, asshown in FIG. 3A, has a magnetically fixed layer 41, a tunnel junctionlayer 42 formed on this magnetically fixed layer 41, and a magneticrecording layer 43. The magnetically fixed layer 41 is formed bystacking a template layer 101, an initial ferromagnetic layer 102, ananti-ferromagnetic layer 103, and a reference ferromagnetic layer 104 inthis order. The magnetic recording layer 43 is formed by stacking a freeferromagnetic layer 105 and a contact layer 106 in this order on thetunnel junction layer 42.

[0055] An MTJ element 31 with the single tunnel junction structure, asshown in FIG. 3B, has a magnetically fixed layer 41, a tunnel junctionlayer 42 formed on this magnetically fixed layer 41, and a magneticrecording layer 43. The magnetically fixed layer 41 is formed bystacking a template layer 101, an initial ferromagnetic layer 102, ananti-ferromagnetic layer 103, a ferromagnetic layer 104′, a nonmagneticlayer 107, and a ferromagnetic layer 104″ in this order. The magneticrecording layer 43 is formed by stacking a ferromagnetic layer 105′, anonmagnetic layer 107, a ferromagnetic layer 105″, and a contact layer106 in this order on the tunnel junction layer 42.

[0056] This MTJ element 31 shown in FIG. 3B has a three-layeredstructure made up of the ferromagnetic layer 104′, the nonmagnetic layer107, and the ferromagnetic layer 104″ in the magnetically fixed layer41, and another three-layered structure made up of the ferromagneticlayer 105′, the nonmagnetic layer 107, and the ferromagnetic layer 105″in the magnetic recording layer 43. Accordingly, compared to the MTJelement 31 shown in FIG. 3A, this MTJ element 31 shown in FIG. 3B canmore suppress the generation of magnetic poles inside the ferromagneticlayers and provide a cell structure more suited to micropatterning.

[0057] An MTJ element 31 with the double tunnel junction structure, asshown in FIG. 4A, has a first magnetically fixed layer 41 a, a firsttunnel junction layer 42 a formed on this first magnetically fixed layer41 a, a magnetic recording layer 43 formed on this first tunnel junctionlayer 42 a, a second tunnel junction layer 42 b formed on this magneticrecording layer 43, and a second magnetically fixed layer 41 b. Thefirst magnetically fixed layer 41 a is formed by stacking a templatelayer 101, an initial ferromagnetic layer 102, an anti-ferromagneticlayer 103, and a reference ferromagnetic layer 104 in this order. Thesecond magnetically fixed layer 41 b is formed by stacking a referenceferromagnetic layer 104, an anti-ferromagnetic layer 103, an initialferromagnetic layer 102, and a contact layer 106 in this order on thesecond tunnel junction layer 42 b.

[0058] An MTJ element 31 with the double tunnel junction structure, asshown in FIG. 4B, has a first magnetically fixed layer 41 a, a firsttunnel junction layer 42 a formed on this first magnetically fixed layer41 a, a magnetic recording layer 43, a second tunnel junction layer 42 bformed on this magnetic recording layer 43, and a second magneticallyfixed layer 41 b. The first magnetically fixed layer 41 a is formed bystacking a template layer 101, an initial ferromagnetic layer 102, ananti-ferromagnetic layer 103, and a reference ferromagnetic layer 104 inthis order. The magnetic recording layer 43 is formed by stacking aferromagnetic layer 43′, a nonmagnetic layer 107, and a ferromagneticlayer 43″ in this order on the first tunnel junction layer 42 a. Thesecond magnetically fixed layer 41 b is formed by stacking a referenceferromagnetic layer 104′, a nonmagnetic layer 107, a ferromagnetic layer104″, an anti-ferromagnetic layer 103, an initial ferromagnetic layer102, and a contact layer 106 in this order on the second tunnel junctionlayer 42 b.

[0059] This MTJ element 31 shown in FIG. 4B has a three-layeredstructure made up of the ferromagnetic layer 43′, the nonmagnetic layer107, and the ferromagnetic layer 43″ forming the magnetic recordinglayer 43, and another three-layered structure made up of theferromagnetic layer 104′, the nonmagnetic layer 107, and theferromagnetic layer 104″ in the second magnetically fixed layer 41 b.Accordingly, compared to the MTJ element 31 shown in FIG. 4A, this MTJelement 31 shown in FIG. 4B can more suppress the generation of magneticpoles inside the ferromagnetic layers and provide a cell structure moresuited to micropatterning.

[0060] The double tunnel junction structure MTJ element 31 suffers lessdeterioration in the MR (Magneto Resistive) ratio (variation inresistance between “1” and “0” states) than the single tunnel junctionstructure MTJ element 31, when the same external bias is applied. Hence,the double tunnel junction structure MTJ element 31 can operate at ahigher bias than the single tunnel junction structure MTJ element 31.This is advantageous in reading out data from a cell.

[0061] The single or double tunnel junction structure MTJ element 31 asdescribed above is formed using the following materials.

[0062] Preferred examples of the material of the magnetically fixedlayers 41, 41 a, and 41 b and the magnetic recording layer 43 are Fe,Co, Ni, and their alloys, magnetite having a large spin polarizability,oxides such as CrO₂ and RXMnO_(3−y) (R; rare earth element, X; Ca, Ba,or Sr), and Heusler alloys such as NiMnSb and PtMnSb. Nonmagneticelements such as Ag, Cu, Au, Al, Mg, Si, Bi, Ta, B, C, 0, N, Pd, Pt, Zr,Ir, W, Mo, and Nb can also be more or less contained in these magneticsubstances, provided that ferromagnetism is not lost.

[0063] As the material of the anti-ferromagnetic layer 103 forming partof these magnetically fixed layers 41, 41 a, and 41 b, it is preferableto use Fe—Mn, Pt—Mn, Pt—Cr—Mn, Ni—Mn, Ir—Mn, NiO, or Fe₂O₃.

[0064] As the material of the tunnel junction layers 42, 42 a, and 42 b,it is possible to use various dielectric substances such as Al₂O₃, SiO₂,MgO, AlN, Bi₂O₃, MgF₂, CaF₂, SrTiO₂, and AlLaO₃. Oxygen, nitrogen, andfluorine deficiencies may be present in these dielectric substances.

[0065]FIGS. 5, 6 and 7 are cross-sectional views illustratingfabrication steps of the magnetic memory device according to the firstembodiment of the invention. A process of manufacturing the magneticmemory device according to the first embodiment will now be described.

[0066] As is shown in FIG. 5, an SOI substrate 14 is prepared. The SOIsubstrate 14 comprises, for example, a P type first semiconductor layer11, a second semiconductor layer 12 and a buried oxide film 13 formedof, e.g. a silicon oxide film. Device isolation regions 15 of an STI(Shallow Trench Isolation) structure are selectively formed from asurface of the second semiconductor layer 12 to a depth reaching theburied oxide film 13. Then, ion implantation and thermal diffusion iseffected in the second semiconductor layer 12, and thus the secondsemiconductor layer 12 of, e.g. P type, is formed. Alternatively, thesecond semiconductor layer 12 may be of N type. A gate electrode 17 isselectively formed on the second semiconductor layer 12, with a gateinsulating film 16 interposed.

[0067] Subsequently, as shown in FIG. 6, a photoresist 18 is coated onthe gate electrode 17 and second semiconductor layer 12, and thephotoresist 18 is patterned as desired. Using the photoresist 18 as amask, ion implantation and thermal diffusion are effected in the secondsemiconductor layer 12. Thereby, a P⁺ type first diffusion layer 19 isformed in that region of the second semiconductor layer 12, which islocated near one end of the gate electrode 17. The photoresist 18 isthen removed.

[0068] As is shown in FIG. 7, a photoresist 20 is coated on the gateelectrode 17 and second semiconductor layer 12, and the photoresist 20is patterned as desired. Using the photoresist 20 as a mask, ionimplantation and thermal diffusion are effected in the secondsemiconductor layer 12. Thereby, a N⁺ type second diffusion layer 21 isformed in that region of the second semiconductor layer 12, which islocated near the other end of the gate electrode 17. Thereafter, thephotoresist 20 is removed.

[0069] Following the above steps, an insulating film 22 is formed on thegate electrode 17, second semiconductor layer 12 and element isolationregions 15, as shown in FIG. 1. Using publicly known art, first tofourth contacts 23 a, 23 b, 25, 27 and 29 and first to third wirings 24a, 24 b, 26, 28 a and 28 b are formed within the insulating film 22. Thefirst to fourth contacts 23 a, 25, 27 and 29 and first to third wirings24 a, 26 and 28 a are connected to the first diffusion layer 19. Thefirst contact 23 b and first wiring 24 b are connected to the seconddiffusion layer 21. The third wiring 28 b functions as write word line.A lower electrode 30 is provided on the fourth contact 29. An MTJelement 31 is formed on that part of the write word line 28 b, which islocated above the write word line 28 b. A bit line 32 is formed on theMTJ element 31.

[0070] Either the first diffusion layer 19 or the second diffusion layer21 may be first formed. Thus, alternatively, the second diffusion layer21 may be first formed.

[0071] According to the first embodiment, the diode 10 is formed usingthe SOI substrate 14. Thus, the second semiconductor layer 12 issurrounded by the buried oxide film 13 (located below the secondsemiconductor layer 12) and the element isolation regions 15 in eachcell. Hence, each cell is electrically isolated from adjacent cells bythe buried oxide film 13 and element isolation regions 15. Therefore,unlike the prior art, there is no need to adjust the depth of the firstand second diffusion layers 19 and 21 for electrical isolation fromadjacent cells, and a variance in diode characteristics can besuppressed.

[0072] In the case where the diode 10 is formed using the SOI substrate14, the first and second diffusion layers 19 and 21 do not extend toadjacent cells while the ion implantation and thermal diffusion arebeing carried out in forming these first and second diffusion layers 19and 21. Therefore, there is no need to keep a long distance betweenadjacent cells, and thus the memory cell size can be reduced.

[0073] It is preferable that the first and second diffusion layers 19and 21 be formed with a predetermined distance X kept therebetween. Ifthe first and second diffusion layers 19 and 21 are formed to contacteach other, a PN junction would be created at the interface thereof anda leak current would flow. The distance X between the first and seconddiffusion layers 19 and 21 may be, for example, equal to a width Y ofthe gate electrode 17. If reduction in area occupied by the memory cellregion is taken into account, it is preferable that the distance X beabout ½ of the width Y of gate electrode 17. In order to make thedistance X between the first and second diffusion layers 19 and 21 lessthan the width Y of the gate electrode 17, as mentioned above, thefollowing method can be adopted: to form the first and second diffusionlayers 19 and 21 before forming a side-wall insulating film on a sidewall of the gate electrode 17 by adjusting the time for heat treatment,and then to form the side-wall insulating film on the side wall of thegate electrode 17.

[0074] In the first embodiment, the second semiconductor layer 12 is ofthe P type. Alternatively, it may be of the N type. It should suffice ifthe impurity concentration in the second semiconductor layer 12 is setto be lower than that in the first diffusion layer 19 or seconddiffusion layer 21.

[0075] [Second Embodiment]

[0076] In a second embodiment of the present invention, the potential ofthe gate electrode formed on the SOI substrate is made variable. Asregards the second embodiment, only differences from the firstembodiment will be described.

[0077]FIG. 8 is a circuit diagram of a magnetic memory device accordingto the second embodiment of the invention. As is shown in FIG. 8, thesecond embodiment differs from the first embodiment in that thepotential of the gate electrode is made variable. Specifically, wherethe second semiconductor layer 12, which will serve as a channel region,is a P type diffusion layer, a negative gate voltage is applied to thegate electrode 17. On the other hand, where the second semiconductorlayer 12, which will serve as a channel region, is an N type diffusionlayer, a positive gate voltage is applied to the gate electrode 17. Thereason why the potential of the gate electrode 17 is made variable willbe explained below.

[0078] The first embodiment employs a diode 10 with a diode structure,which is generally called a “gate control” diode structure. The I-Vcharacteristics of the diode 10 will vary depending on the gate voltage.This phenomenon is caused by an interface level that is present underthe gate electrode 17. Normally, a depletion layer is created under thegate electrode 17 in accordance with a voltage applied to the gateelectrode 17. In this case, if an interface level is present in thedepletion layer, the interface level functions as a center of junctionand a reverse bias current is caused to flow. In general terms, thehigher the gate voltage on the positive side, the greater the width ofthe depletion layer and the higher the reverse bias current.

[0079] In the case where the second semiconductor layer 12, which willfunction as the channel region under the gate electrode 17, is the Ptype diffusion layer, as shown in FIG. 1 (the first embodiment), a PNjunction between the N⁺ type second diffusion layer 21 and the P typesecond semiconductor layer 12 will be a problem. In order to prevent theoccurrence of a reverse bias current due to the interface level, itshould suffice to set the gate voltage to have a negative value. On theother hand, where the second semiconductor layer 12, which will functionas the channel region under the gate electrode 17, is the N typediffusion layer, it should suffice if the gate voltage is set to have apositive value. In the second embodiment, in order to prevent theoccurrence of a reverse bias current due to the interface level, thepotential of the gate electrode 17 is made variable in this manner.

[0080] According to the second embodiment, the same advantages as withthe first embodiment can be obtained.

[0081] Furthermore, the gate voltage to be applied to the gate electrode17 is selectively set to have a positive value or a negative value inaccordance with the conductivity type of the second semiconductor layer12 functioning as the channel region. Thereby, the occurrence of thereverse bias current due to the interface level can be prevented.

[0082] [Third Embodiment]

[0083] A third embodiment of the invention relates to a structurewherein an SOI substrate is used for the memory cell array region and abulk substrate is used for the peripheral circuit region. As regards thethird embodiment, only differences from the first embodiment will beexplained.

[0084]FIGS. 9A and 9B are cross-sectional views showing a magneticmemory device according to a third embodiment of the invention. As isshown in FIG. 9, in the magnetic memory device according to the thirdembodiment, the SOI substrate 14 is not used for both the memory cellarray region and peripheral circuit region. A bulk substrate 51 is usedfor the peripheral circuit region alone. Specifically, in the memorycell array region, like the first embodiment, the diode 10 is formedusing the SOI substrate 14. On the other hand, in the peripheral circuitregion, the bulk substrate 51 is used and a peripheral transistor 52 isformed on the bulk substrate 51.

[0085] As shown in FIG. 9A, the surface of the bulk substrate 51 issubstantially on a level with the surface of the first semiconductorlayer 11 of SOI substrate 14. Accordingly, there is a stepped portion ata boundary between the memory cell array region and peripheral circuitregion, and the level of the gate electrode 17 in the memory cell arrayregion differs from that of a gate electrode 53 in the peripheralcircuit region.

[0086] As shown in FIG. 9B, the surface of the bulk substrate 51 issubstantially on a level with the surface of the second semiconductorlayer 12 of SOI substrate 14. Accordingly, there is not the steppedportion at the boundary between the memory cell array region andperipheral circuit region, and the gate electrode 17 in the memory cellarray region is substantially on a level with the gate electrode 53 inthe peripheral circuit region.

[0087]FIGS. 10A through 11C are cross-sectional views illustratingfabrication steps of the magnetic memory device according to the thirdembodiment of the invention. Two methods for fabricating the SOIsubstrate in the memory cell array region alone will now be described.

[0088] The steps of a first method will first be described referring toFIGS. 10A, 10B and 10C. As is shown in FIG. 10A, a silicon oxide film 2serving as a mask layer is provided on, e.g. a P type silicon substrate1 in the memory cell array region and peripheral circuit region. Aphotoresist 3 is formed on the silicon oxide film 2, and it is patternedso as to remain only in the memory cell array region. Next, as shown inFIG. 10B, using the photoresist 3 as a mask, the silicon oxide film 2 isselectively etched, following which the photoresist 3 is removed. Usingthe silicon oxide film 2 as a mask, O⁺ ions, for instance, are implantedonly in the peripheral circuit region. Thereafter, the silicon oxidefilm 2 is removed. Then, as shown in FIG. 10C, a buried oxide film 13 isformed in the memory cell array region alone by annealing. Thus, the SOIsubstrate 14 is formed.

[0089] The steps of a second method will now be described referring toFIGS. 11A, 11B and 11C. As is shown in FIG. 11A, an SOI substrate 14 isformed, which comprises first and second semiconductor layers 11 and 12and a buried oxide film 13 formed between the first and second first andsecond semiconductor layers 11 and 12. A photoresist 3 is formed on thesecond semiconductor layer 12, and it is patterned to remain only in thememory cell array region. Using the photoresist 3 as a mask, as shown inFIG. 11B, the second semiconductor layer 12 and buried oxide film 13 inthe peripheral circuit region are etched. Then, as shown in FIG. 11C,the photoresist 3 is removed. The SOI substrate 14 is thus left only inthe memory cell array region.

[0090] Following the step of FIG. 11C, the stepped portion between thememory cell array region and peripheral circuit region may be eliminatedby the following method. For example, as shown in FIG. 11D, a siliconnitride film 4 is deposited on the entire surface of the memory cellarray region and peripheral circuit region, and only that portion of thesilicon nitride film 4, which lies on the peripheral circuit region, isremoved by a lithography technique. Then, as shown in FIG. 11E, Si onthe exposed surface is selectively grown up to a level substantiallycorresponding to the surface level of the second semiconductor layer 12by means of selective epitaxial growth (SEG). Thereby, an epitaxialgrowth layer 5 is formed in the peripheral circuit region. The siliconnitride film 4 on the second semiconductor layer 12 is removed, as shownin FIG. 11F.

[0091] According to the third embodiment, the following advantage aswell as the advantages of the first embodiment can be obtained.

[0092] In general, a body contact needs to be added to a transistor in aCMOS circuit formed on the SOI substrate 14. The provision of the bodycontact will disadvantageously increase the chip area. In the thirdembodiment, however, the SOI substrate 14 is used for the memory cellarray region, but the bulk substrate 51 is used for the peripheralcircuit region. As a result, there is no need to add a body contact tothe peripheral transistor 52, and the chip area can be reduced, comparedto the case where the SOI substrate is used for both the memory cellarray region and peripheral circuit region.

[0093] The voltage to be applied to the gate electrode of the memorycell array region according to the third embodiment may be madevariable, similarly with the second embodiment. In this case, the sameadvantages as with second and third embodiments can be obtained.

[0094] [Fourth Embodiment]

[0095] In the first to third embodiments, double-axis data write usingwrite word lines and bit lines is performed. By contrast, in a fourthembodiment, single-axis data write using bit lines alone is performed.

[0096]FIG. 12 is a plan view of a magnetic memory device according tothe fourth embodiment of the invention. FIG. 13A is a cross-sectionalview of the magnetic memory device, taken along line XIIIA-XIIIA in FIG.12. FIG. 13B is a cross-sectional view of the magnetic memory device,taken along line XIIIB-XIIIB in FIG. 12. FIG. 14 is a circuit diagram ofthe magnetic memory device according to the fourth embodiment of theinvention. As regards the fourth embodiment, only differences instructure from the first embodiment will be described.

[0097] As is shown in FIGS. 12, 13A, 13B and 14, a memory cell in themagnetic memory device according to the fourth embodiment is composed ofan MTJ element, transistors Tr1 and Tr2 for data write, a transistor Tr3for data read-out, and bit lines BL1, BL2 and BLC1.

[0098] Specifically, two transistors Tr1 and Tr2, which are switchingelements for data write, are formed on the SOI substrate 14.

[0099] The gate electrode of the transistor Tr1 functions as a dataread-out/write word line WL1. One of the diffusion layers of thetransistor Tr1 is connected to the bit-line connection wiring BLC1 via ametal wiring ML1, a contact C1, etc. The other diffusion layer oftransistor Tr1 is connected to the bit line BL1 via a metal wiring ML3,a contact C3, etc.

[0100] The gate electrode of the transistor Tr2 functions as a writeword line WWL1. One of the diffusion layers of the transistor Tr2 isconnected to the bit-line connection wiring BLC1 via the metal wiringML2, contact C2, etc. The other diffusion layer of transistor Tr2 isconnected to the bit line BL2 via a metal wiring ML5, a contact C5, etc.

[0101] The MTJ element is connected at one end to the bit-lineconnection wiring BLC1, and at the other end to a ground (GND) line. Thetransistor Tr3, which is a switching element for data read-out, may beconnected to the MTJ element.

[0102] In this embodiment, a single write wiring is used. Thus, thedirection of magnetization is made easily reversible by shifting theangle of intersection between the direction of extension of the bit-lineconnection wiring BLC1, which is the write wiring, and the magnetizationdirection of the MTJ element, by a certain degree (e.g. 45°) from 90°.

[0103] In the single-axis data write magnetic memory device, asdescribed above, the data write/read operations are performed asfollows.

[0104] When data is to be written in the MTJ element, the word line WL1and write word line WWL1, which are the gate electrodes of thetransistors Tr1 and Tr2 of the selected cell, are turned on. A writecurrent is let to flow from the bit line BL1 to the bit line BL2, orvice versa. A magnetic field produced by the write current changes themagnetization direction of the recording layer of the MTJ element. Thedirection of current may be chosen in accordance with the magnetizationdirection to be changed. During the write operation, the transistor Tr3connected to the common GND line is turned off, thereby to prevent thewrite current from flowing to the MTJ element.

[0105] On the other hand, when data is to be read out of the MTJelement, the word line WL1 of the transistor Tr1 of the selected cell isturned on, and all the write word lines WWL1, 2, . . . , are turned off.A read-out current is let to flow from the bit line BL1 to the groundGND via the MTJ element, and the data is read by a sense amplifierconnected to the bit line BL1. During the read-out operation, thetransistor Tr3 connected to the common GND line is turned on.

[0106] According to the fourth embodiment, the following advantage, aswell as the advantages of the first embodiment, can be obtained.

[0107] In the case of the structure for double-axis data write usingwrite word lines and bit lines, a plurality of bit lines and word linesare provided in a matrix and MTJ elements are disposed at intersectionsof the bit lines and word lines. In the write operation, data write iseffected not only on one MTJ element located at the intersection of theselected bit line and selected word line, but also on an MTJ elementlocated below the selected bit line or above the selected word line. Inshort, in the case of the double-axis data write, there is a possibilityof erroneous write in a semi-selected cell.

[0108] By contrast, in the fourth embodiment, the transistors Tr1 andTr2 are arranged so that a current may flow to only the bit lines BL1and BL2 in the data write operation. Hence, a write current does notflow to cells other than the selected cell, and there is nosemi-selected cell. Therefore, a disturb defect (data retention defect)in a semi-selected cell can be prevented.

[0109] In the first to third embodiments, the diode is used as aswitching element, but the diode may be replaced with a transistor. Inthe fourth embodiment, diodes may be substituted for the transistorsTr1, Tr2 and Tr3.

[0110] In the first to fourth embodiments, the MTJ element is used as amemory element. Alternatively, the MTJ element may be replaced with aGMR (Giant Magneto-Resistive) element comprising two magnetic layers anda conductive layer interposed therebetween.

[0111] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A magnetic memory device comprising: an SOIsubstrate having a first semiconductor layer, a first insulating filmformed on the first semiconductor layer, and a second semiconductorlayer formed on the first insulating film; an element isolationinsulating film formed selectively in the second semiconductor layer andextending from a surface of the second semiconductor layer with a depthreaching the first insulating film; a switching element formed in thesecond semiconductor layer; a magneto-resistive element connected to theswitching element; a first wiring extending in a first direction at adistance below the magneto-resistive element; and a second wiring formedon the magneto-resistive element and extending in a second directiondifferent from the first direction.
 2. A magnetic memory deviceaccording to claim 1, wherein the switching element is a diode.
 3. Amagnetic memory device according to claim 2, wherein the diodecomprises: a gate electrode formed on the second semiconductor layerwith a gate insulating film interposed; a first diffusion layer of afirst conductivity type that is formed in a portion of the secondsemiconductor layer, which is located near one end of the gateelectrode, the first diffusion layer being connected to themagneto-resistive element; and a second diffusion layer of a secondconductivity type that is formed in a portion of the secondsemiconductor layer, which is located near the other end of the gateelectrode.
 4. A magnetic memory device according to claim 3, wherein thesecond diffusion layer is provided spaced apart from the first diffusionlayer.
 5. A magnetic memory device according to claim 3, wherein adistance between the first and second diffusion layers is substantiallyequal to a width of the gate electrode.
 6. A magnetic memory deviceaccording to claim 3, wherein a distance between the first and seconddiffusion layers is ½ of a width of the gate electrode.
 7. A magneticmemory device according to claim 4, wherein the second semiconductorlayer lying between the first diffusion layer and the second diffusionlayer is a third diffusion layer of the first conductivity type or thesecond conductivity type.
 8. A magnetic memory device according to claim7, wherein the third diffusion layer has an impurity concentration lowerthan an impurity concentration of the first diffusion layer or thesecond diffusion layer.
 9. A magnetic memory device according to claim3, wherein a potential to be applied to the gate electrode is fixed. 10.A magnetic memory device according to claim 3, wherein a potential to beapplied to the gate electrode is fixed at a ground potential level. 11.A magnetic memory device according to claim 3, wherein a potential to beapplied to the gate electrode is variable.
 12. A magnetic memory deviceaccording to claim 7, wherein a negative voltage is applied to the gateelectrode in a case where the third diffusion layer is of a P type, anda positive voltage is applied to the gate electrode in a case where thethird diffusion layer is of an N type.
 13. A magnetic memory deviceaccording to claim 1, further comprising a peripheral circuit regionformed using a bulk substrate, located at a periphery of a memory cellarray region including the magneto-resistive element and the switchingelement, and having a peripheral circuit controlling the switchingelement.
 14. A magnetic memory device according to claim 13, wherein asurface of the bulk substrate is substantially on a level with a surfaceof the first semiconductor layer.
 15. A magnetic memory device accordingto claim 13, further comprising: an epitaxial growth layer formed on thebulk substrate, the epitaxial growth layer having a surface that is on alevel with a surface of the second semiconductor layer; and a secondinsulating film formed between the epitaxial growth layer and the secondsemiconductor layer.
 16. A magnetic memory device comprising: an SOIsubstrate having a first semiconductor layer, a first insulating filmformed on the first semiconductor layer, and a second semiconductorlayer formed on the first insulating film; an element isolationinsulating film formed selectively in the second semiconductor layerextending from a surface of the second semiconductor layer with a depthreaching the first insulating film; a first switching element formed inthe SOI substrate and having one end and the other end; a secondswitching element formed in the SOI substrate and having one end and theother end; a first wiring connected to said one end of the firstswitching element; a second wiring connected to said one end of thesecond switching element; a third wiring connected to said other end ofthe first switching element and said other end of the second switchingelement; and a magneto-resistive element connected to the third wiring.17. A magnetic memory device according to claim 16, wherein a directionof magnetization of the magneto-resistive element is inclined 45° withrespect to a direction of extension of the third wiring.
 18. A magneticmemory device according to claim 16, wherein a gate electrode of thefirst switching element is a word line for data write and data read-out.19. A magnetic memory device according to claim 16, wherein a gateelectrode of the second switching element is a word line for data write.20. A magnetic memory device according to claim 16, further comprising athird switching element connected to the magneto-resistive element. 21.A magnetic memory device according to claim 20, wherein a gate electrodeof the third switching element is a word line for data read-out.
 22. Amagnetic memory device according to claim 16, wherein themagneto-resistive element is connected to a ground.
 23. A magneticmemory device according to claim 16, wherein each of the first andsecond switching elements is a transistor or a diode.
 24. A magneticmemory device according to claim 20, wherein the third switching elementis a transistor or a diode.
 25. A magnetic memory device according toclaim 16, wherein when data is written in the magneto-resistive element,the first and second switching elements are turned on to let a currentflow between the first and second wirings.
 26. A magnetic memory deviceaccording to claim 25, further comprising a third switching elementconnected to the magneto-resistive element, wherein the third switchingelement is turned off when the data is written.
 27. A magnetic memorydevice according to claim 16, wherein when data is read out from themagneto-resistive element, the first switching element is turned on andthe second switching element is turned off to let a current flow fromthe first wiring to the magneto-resistive element.
 28. A magnetic memorydevice according to claim 27, further comprising a third switchingelement connected to the magneto-resistive element, wherein the thirdswitching element is turned on when the data is read out.
 29. A magneticmemory device according to claim 1, wherein the magneto-resistiveelement is an MTJ element comprising at least a first magnetic layer, asecond magnetic layer and a non-magnetic layer.
 30. A magnetic memorydevice according to claim 29, wherein the MTJ element has a singlejunction structure having one said non-magnetic layer, or a doublejunction structure having two said non-magnetic layers.
 31. A method ofmanufacturing a magnetic memory device, comprising: forming an SOIsubstrate having a first semiconductor layer, a first insulating filmformed on the first semiconductor layer, and a second semiconductorlayer formed on the first insulating film; forming an element isolationinsulating film selectively in the second semiconductor layer, theelement isolation insulating film extending from a surface of the secondsemiconductor layer with a depth reaching the first insulating film;forming a switching element in the second semiconductor layer; forming afirst wiring extending in a first direction; forming a magneto-resistiveelement connected to the switching element at a distance above the firstwiring; and forming a second wiring on the magneto-resistive element,the second wiring extending in a second direction different from thefirst direction.
 32. A method of manufacturing a magnetic memory device,according to claim 31, wherein the switching element is a diode.
 33. Amethod of manufacturing a magnetic memory device, according to claim 32,wherein the forming of the diode comprises: forming a gate electrode onthe second semiconductor layer with a gate insulating film interposed;forming a first diffusion layer of a first conductivity type in aportion of the second semiconductor layer, which is located near one endof the gate electrode, the first diffusion layer being connected to themagneto-resistive element; and forming a second diffusion layer of asecond conductivity type in a portion of the second semiconductor layer,which is located near the other end of the gate electrode.
 34. A methodof manufacturing a magnetic memory device, according to claim 33,wherein the second diffusion layer is provided spaced apart from thefirst diffusion layer.
 35. A method of manufacturing a magnetic memorydevice, according to claim 34, wherein impurities are implanted in thesecond semiconductor layer between the first diffusion layer and thesecond diffusion layer to form a third diffusion layer of the firstconductivity type or the second conductivity type.
 36. A method ofmanufacturing a magnetic memory device, according to claim 35, whereinthe third diffusion layer is formed to have an impurity concentrationlower than an impurity concentration of the first diffusion layer or thesecond diffusion layer.
 37. A method of manufacturing a magnetic memorydevice, according to claim 33, wherein the first and second diffusionlayers are formed that a distance between the first and second diffusionlayers is substantially equal to a width of the gate electrode.
 38. Amethod of manufacturing a magnetic memory device, according to claim 33,wherein the first and second diffusion layers are formed that a distancebetween the first and second diffusion layers is ½ of a width of thegate electrode.
 39. A method of manufacturing a magnetic memory device,according to claim 31, further comprising: forming a memory cell arrayregion using the SOI substrate and a peripheral circuit region using abulk substrate.
 40. A method of manufacturing a magnetic memory device,according to claim 39, further comprising: forming a mask layer on asubstrate in the memory cell array region; implanting ions in thesubstrate in the peripheral circuit region, using the mask layer as amask; and forming the first insulating film in the substrate in thememory cell array region to form the SOI substrate in the memory cellarray region and the bulk substrate in the peripheral circuit region.41. A method of manufacturing a magnetic memory device, according toclaim 39, further comprising: forming the SOI substrate in the memorycell array region and the peripheral circuit region; and removing thefirst insulating film and the second semiconductor layer from theperipheral circuit region to form the SOI substrate in the memory cellarray region and forming the bulk substrate in the peripheral circuitregion.
 42. A method of manufacturing a magnetic memory device,according to claim 41, further comprising: forming a second insulatingfilm on the SOI substrate and the bulk substrate; removing part of thesecond insulating film from the peripheral circuit region to expose asurface of the bulk substrate; forming an epitaxial growth layer on thebulk substrate; and removing the second insulating film on the secondsemiconductor layer to make a level of a surface of the epitaxial growthlayer equal to a level of a surface of the second semiconductor layer.43. A method of manufacturing a magnetic memory device, comprising:forming an SOI substrate having a first semiconductor layer, a firstinsulating film formed on the first semiconductor layer, and a secondsemiconductor layer formed on the first insulating film; forming anelement isolation insulating film selectively in the secondsemiconductor layer, the element isolation insulating film extendingfrom a surface of the second semiconductor layer with a depth reachingthe first insulating film; forming first and second switching elementsin the SOI substrate, each of the first and second switching elementshaving one end and the other end; forming a magneto-resistive elementabove the SOI substrate; and forming first to third wirings, the firstwiring being connected to said one end of the first switching element,the second wiring being connected to said one end of the secondswitching element, and the third wiring being connected to said otherend of the first switching element, said other end of the secondswitching element and the magneto-resistive element.
 44. A method ofmanufacturing a magnetic memory device, according to claim 43, whereinthe magneto-resistive element and the third wiring are formed that adirection of magnetization of the magneto-resistive element is inclined45° with respect to a direction of extension of the third wiring.
 45. Amethod of manufacturing a magnetic memory device, according to claim 43,wherein each of the first and second switching elements is a transistoror a diode.
 46. A method of manufacturing a magnetic memory device,according to claim 43, further comprising: forming a third switchingelement connected to the magneto-resistive element.
 47. A method ofmanufacturing a magnetic memory device, according to claim 46, whereinthe third switching element is a transistor or a diode.
 48. A method ofmanufacturing a magnetic memory device, according to claim 43, whereinthe magneto-resistive element is an MTJ element comprising at least afirst magnetic layer, a second magnetic layer and a non-magnetic layer.